1. Field of the Invention
This present invention relates generally to the field of integrated circuit design and, more specifically, to an input buffer circuit that achieves high performance with reduced power consumption.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Computer systems and other electronic devices typically include a variety of electrically interconnected integrated circuit (IC) packages which perform a variety of functions, including memory and processing functions. Many integrated circuit devices have input buffers, which receive data from outside of the integrated circuit. The input buffer is the first stop for data inside the integrated circuit before the data is stored or further processed. Typically, one input buffer is used for each data input of an integrated circuit.
An individual bit of data (a logic high (“1”) or a logic low (“0”) may be presented on each of the data input lines. When the data on the input lines has become stable, each bit is transferred into the corresponding input buffer for that data line. A typical method of transferring data from the input lines into the input buffer is through the use of a CLOCK signal. The CLOCK signal is a recurring signal (typically a square wave) that is used to synchronize the operation of a wide range of functions within an integrated circuit. When the data becomes stable on the input lines, the next rising clock edge may be used to signal the input buffer to load the data that is present on the input lines. The data may then be transferred from the input lines into the input buffer itself.
Two important factors in the design of input buffers are power consumption and speed of operation (performance). The relationship between power consumption and performance is a classic design tradeoff. This means that an input buffer that is optimized for performance (high speed) typically consumes much more power than an input buffer designed to save power. Correspondingly, an input buffer that is designed to conserve power typically has slower performance characteristics compared to an input buffer that is designed for high performance.
As computer systems become faster, designers of integrated circuits are striving to produce input buffers that have the fastest performance. Input buffer performance is important because the speed at which an input buffer is able to receive data has a direct impact on the overall speed of the integrated circuit to process information. Unfortunately, designers are also faced with steadily decreasing power consumption requirements. Power consumption goals are being driven down because users of computers and other electronic devices that incorporate integrated circuits are demanding increasingly small package sizes and longer battery life.
One way to reduce input buffer power consumption is to turn power off to the input buffer when it is not in use. A known method is to turn the input buffer completely off after it has latched data and turn it on again prior to latching the next successive data. In input buffers where data is latched on the rising edge of a CLOCK signal, the input buffer is turned off when the CLOCK signal goes high because it is known that the data has been received during the transition of the CLOCK signal from a logic low (“0”) to a logic high (“1”). The input buffer may be turned on again when the clock goes low because it is known that the next successive input data for the input buffer will arrive and stabilize when the clock is low in anticipation of being latched when the clock transitions from low to high.
There is, however, a problem with turning the input buffers completely off when the CLOCK signal is high. The problem is that input buffers take time to get ready when power is reapplied to them. If the buffer is not ready when the next successive data input comes in, then the speed at which the incoming data transfers through the input buffer may slow down or incoming data may be lost altogether. Accordingly, an input buffer that offers relatively high performance in terms of operational speed but consumes less power is desirable.